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E2E0057-29-71
Semiconductor ML63512A/63514A
Semiconductor
This ML63512A/63514A version: Jul. 1999 Previous version: Jun. 1999
4-Bit Microcontroller with Built-in Level Detector, Melody Circuit, and Comparator, Operating at 0.9 V (Min.)
GENERAL DESCRIPTION
The ML63512A/63514A is a CMOS 4-bit microcontroller with built-in level detector and operates at 0.9 V (min.). The ML63512A/63514A is an M6351x series mask ROM-version product of OLMS-63K family, which employs Oki's original CPU core nX-4/250. The program memory capacity and data memory capacity of the ML63512A differ from those of the ML63514A. 48-pin TQFP and 64-pin TQFP packages are available for the ML63512A and ML63514A.
FEATURES
* Extensive instruction set 407 instructions Transfer, rotate, increment/decrement, arithmetic operations, comparison, logic operations, mask operations, bit operations, ROM table reference, stack operations, flag operations, jump, conditional branch, call/return, control. * Wide variety selection of addressing modes Indirect addressing of four data memory types, with current bank register, extra bank register, HL register and XY register. Data memory bank internal direct addressing mode. * Processing speed Two clocks per machine cycle, with most instructions executed in one machine cycle. Minimum instruction execution time : 61 ms (@ 32.768 kHz system clock) 1 ms (@ 2 MHz system clock) * Clock generation circuit Low-speed clock High-speed clock
: Crystal oscillation or RC oscillation selectable by mask option (30 to 80 kHz) : Ceramic oscillation or RC oscillation selectable by mask option (2 MHz max.)
* Program memory space ML63512A: 4K words ML63514A: 8K words Basic instruction length is 16 bits/1 word * Data memory space ML63512A: 128 nibbles ML63514A: 256 nibbles
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Semiconductor * Stack level Call stack level Register stack level
ML63512A/63514A
: 16 levels : 16 levels
* I/O ports Input ports: Selectable as input with pull-up resistor/high-impedance input Output ports: N-channel open drain output (can directly drive LEDs) Input-output ports: Selectable as input with pull-up resistor/high-impedance input Selectable as N-channel open drain output/CMOS output Can be interfaced with external peripherals that use a different power supply than this device uses. (Power to the output port is supplied from VDDI (separate power suply)) Number of ports: (For 48-pin packages) Input port : 1 port 4 bits Output port : 1 port 4 bits Input-output port : 6 ports 4 bits (For 64-pin packages) Input port : 1 port 4 bits Output port : 1 port 4 bits Input-output port : 9 ports 4 bits * Melody output function Melody sound frequency Tone length Tempo Melody data Number of ports Buzzer driver signal output * Level detector Conversion time Dedicated input pins Detection level * Comparator Offset voltage Comparison time Number of channels
: : : : : :
529 to 2979 Hz (@ 32.768 kHz) 63 varieties 15 varieties Stored in the program memory 1 (dedicated pin) 4 kHz (@ 32.768 kHz)
: Approx. 183 ms (@ 32.768 kHz) : 2 pins (switched by software; for the secondary functions of the input ports) : 12 levels
: 50 mV max. (VDD = 1.5 V) : Approx. 183 ms (@ 32.768 kHz) : 1 (for the secondary functions of the input ports)
* Reset function Reset through RESETB pin (RESETB pin can be pulled up by mask option) * Power supply backup Backup circuit (voltage multiplier) enables operation at 0.9 V minimum
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* Timers and counter 8-bit timer 2 Selectable as auto-reload mode/capture mode/clock frequency measurement mode 15-bit time base counter 1 1 Hz, 2 Hz, 4 Hz, 8 Hz, 16 Hz, 32 Hz, 64 Hz, 128 Hz, 256 Hz, 512 Hz, 1 kHz, and 2 kHz signals can be read (@ 32.768 kHz) * Serial port Mode UART communication speed
Clock frequency in synchronous mode Data length * Interrupt sources External interrupt (4 sources) Internal interrupt (10 sources)
: Selectable as UART mode/synchronous mode : 2TBCCLK, TBCCLK, 1/2TBCCLK, Timers 0 & 1 overflow 24 kbps Max. (when 2TBCCLK @ 80 kHz selected) : 30 to 80 kHz (internal clock mode), external clock frequency : 5 to 8 bits
: Selectable as rising edge/falling edge/both rising and falling edges : Time base interrupt 4 (2, 4, 16, and 32 Hz @ 32.768 kHz) Timer interrupt 2 Level detector interrupt 1 Serial port reception interrupt 1 Serial port transmission interrupt 1 Melody end interrupt 1
* Operating Temperature -20 to +70C * Supply voltage When backup used When backup not used
: 0.9 to 1.8 V (Maximum operating frequency 1 MHz) : 1.8 to 3.5 V (When Level detector or Comparator is used, maximum operating frequency 2 MHz) 1.8 to 5.5 V (When Level detector and Comparator are not used, maximum operating frequency 2 MHz)
* Package options: 48-pin plastic TQFP (TQFP48-P-0707-0.50-K) : (Product name: ML63512A-xxxTB, ML63514A-xxxTB) 64-pin plastic TQFP (TQFP64-P-1010-0.50-K) : (Product name: ML63512A-xxxTP, ML63514A-xxxTP) xxx indicates a code number.
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Semiconductor
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BLOCK DIAGRAM
An asterisk (*) indicates the port secondary function. The power to the circuits corresponding to the signal names inside is supplied from V DDI (power supply for interface).
nX-4/250
CBR H L RA PC ROM ML63512A: 4KW ML63514A: 8KW
TIMING CONTROL
EBR
X
Y C
A G MIE Z BUS CONTROL
SP RSP
ALU
STACK CAL: 16-level REG: 16-level
INSTRUCTION DECODER
IR
INT 2 RESETB RST RAM ML63512A: 128N ML63514A: 256N INT TST1B TST2B TST INT 2 SIO INT 1 OSC MELODY INT 4 TBC MD TIMER 8bit 2 TM0CAP/TM1CAP* TM0OVF/TM1OVF* T0CK* T1CK* RXC* TXC* RXD* TXD*
DATA BUS
XT0 XT1 OSC0 OSC1 TBCCLK* HSCLK*
P0.0-P0.3 P1.0-P1.3 P2.0-P2.3 P3.0-P3.3 I/O PORT P4.0-P4.3 P5.0-P5.3 P6.0-P6.3=
INT 1 LDIN0* LDIN1* Level Detector
CMPIN* CMPREF*
CMP
VDDH VDD
CB1 CB2
BACKUP
INT 4
P9.0-P9.3= PA.0-PA.3=
VDDL
VR
INPUT PORT
P7.0-P7.3
OUTPUT PORT
P8.0-P8.3
VDDI VSS
=Port 6 (P6.0 to P6.3), Port 9 (P9.0 to P9.3) and Port A (PA.0 to PA.3) are only provided for the 64-
pin packages. 4/29
P3.0/RXD
P3.2/RXC P3.1/TXC
P3.3/TXD
Semiconductor
P5.3 9 8 7 6 5 4 3 2 1 12
48 P2.3 47 P2.2 46 P2.1/HSCLK 45 P2.0/TBCCLK 44 P1.3/T1CK
P5.2 11 10
P5.1
P5.0
P4.1
P4.0
P4.2 P4.3
P7.0/CMPIN 13 P7.1/CMPREF 14 P7.2/LDIN0 15 P7.3/LDIN1 16 P8.0 17 P8.1 18 P8.2 19 P8.3 20 VDDI 21 VSS 22 VDD VDDH 24 23
PIN CONFIGURATION (TOP VIEW)
43 P1.2/T0CK 42 P1.1/TM1CAP/TM1OVF 41 P1.0/TM0CAP/TM0OVF 40 P0.3/INT3 39 P0.2/INT2 38 P0.1/INT1 37 P0.0/INT0
48-Pin Plastic TQFP
36 MD 32 VSS 28 XT0 29 XT1 25 CB1 26 CB2 27 VDDL 33 OSC0 34 OSC1 30 TST1B 31 TST2B 35 RESETB
ML63512A/63514A
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PIN CONFIGURATION (TOP VIEW) (continued)
56 P1.1/TM1CAP/TM1OVF 55 P1.0/TM0CAP/TM0OVF
59 P2.0/TBCCLK 58 P1.3/T1CK
60 P2.1/HSCLK
57 P1.2/T0CK
54 P0.3/INT3
53 P0.2/INT2
52 P0.1/INT1
51 P0.0/INT0
64 PA.1
63 PA.0
62 P2.3
61 P2.2
50 P9.3
PA.2 PA.3 P3.0/RXD P3.1/TXC P3.2/RXC P3.3/TXD P4.0 P4.1 P4.2 P4.3 P5.0 P5.1 P5.2 P5.3 P6.0 P6.1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
49 P9.2
48 P9.1 47 P9.0 46 MD 45 RESETB 44 OSC1 43 OSC0 42 VSS 41 TST2B 40 TST1B 39 XT1 38 XT0 37 VDDL 36 CB2 35 CB1 34 (NC) 33 (NC)
P6.2 17
P6.3 18
P7.0/CMPIN 19
P7.1/CMPREF 20
P7.2/LDIN0 21
P7.3/LDIN1 22
P8.0 23 P8.1 24
P8.2 25
P8.3 26
VDDI 27
VSS 28
VDD 29
VDDH 30
(NC) 31
64-Pin Plastic TQFP Note: Pins marked as (NC) are no-connection pins which are left open.
(NC) 32
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PIN DESCRIPTIONS
The basic functions of each pin of the ML63512A/63514A are described in Table 1. A symbol with a slash (/) denotes a pin that has a secondary function. Refer to Table 2 for secondary functions. For type, "--" denotes a power supply pin, "I" an input pin, "O" an output pin, and "I/O" an inputoutput pin. For pin, "TB" denotes a 48-pin flat package (48TQFP), and "TP" a 64-pin flat package (64TQFP). Table 1 Pin Descriptions (Basic Functions)
Function Symbol VDD VSS VDDI Power Supply VDDH CB1 CB2 XT0 24 25 26 28 30 35 36 38 -- -- -- I VDDL Pin TB 23 21 27 TP 29 27 37 Type -- -- -- -- Positive power supply Negative power supply Positive power supply pin for external interface (PORT8 supply) Positive power supply pin for internal logic (internally generated). A capacitor Cl (0.1 mF) should be connected between this pin and VSS. Voltage multiplier pin for power supply backup (internally generated). A capacitor Ch (1.0 mF) should be connected between this pin and VSS. Pins to connect a capacitor for voltage multiplier. A capacitor (1.0 mF) should be connected between CB1 and CB2. Low-speed clock oscillation pins. Crystal oscillation or RC oscillation is selected by the mask option. If crystal oscillation is selected, connect a crystal between XT0 and XT1, and connect capacitor (CG) between XT0 and VSS. XT1 Oscillation OSC0 33 43 I 29 39 O If RC oscillation is selected, connect external oscillation resistor (RCRL) between XT0 and XT1. High-speed clock oscillation pins. Ceramic oscillation or RC oscillation is selected by the mask option. If ceramic oscillation is selected, connect a ceramic resonator between OSC0 and OSC1, and connect capacitor (CL0, CL1) between OSC0 and VSS, OSC1 and VSS. OSC1 34 44 O If RC oscillation is selected, connect external oscillation resistor (RCRH) between OSC0 and OSC1. Test TST1B TST2B 30 31 40 41 I I Input pins for testing. A pull-up resistor is internally connected to these pins. Reset input pin. Setting this pin to "L" level puts this device into a reset state. Reset RESETB 35 45 I Then, setting this pin to "H" level starts executing an instruction from address 0000H. An internal or external pull-up resistor is selected by mask option. Melody MD 36 46 O Melody output pin (non-inverted output) Description
22, 32 28, 42
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Semiconductor
ML63512A/63514A
Table 1 Pin Descriptions (Basic Functions) (continued)
Pin TB 37 38 39 40 41 TP 51 52 53 54 55 I/O
Function
Symbol P0.0/INT0 P0.1/INT1 P0.2/INT2 P0.3/INT3 P1.0/ TM0CAP/ TM0OVF P1.1/ TM1CAP/ TM1OVF P1.2/T0CK P1.3/T1CK P2.0/TBCCLK P2.1/HSCLK P2.2 P2.3 P3.0/RXD P3.1/TXC P3.2/RXC P3.3/TXD P4.0 P4.1 P4.2 P4.3 P5.0 P5.1 P5.2 P5.3
Type
Description 4-bit input-output ports. In input mode, pull-up resistor input or high-impedance input is selectable for each bit. In output mode, N-channel open drain output or CMOS output is selectable for each bit.
42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11 12
56 57 58 59 60 61 62 3 4 5 6 7 8 9 10 11 12 13 14
I/O
Port
I/O
I/O
I/O
I/O
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Semiconductor
ML63512A/63514A
Table 1 Pin Descriptions (Basic Functions) (continued)
Pin TB -- -- -- -- 13 14 15 16 17 18 19 20 -- -- -- -- -- -- -- -- TP 15 16 I/O P6.2 P6.3 P7.0/CMPIN P7.1/CMPREF P7.2/LDIN0 P7.3/LDIN1 Port P8.0 P8.1 P8.2 P8.3 P9.0 P9.1 P9.2 P9.3 PA.0 PA.1 PA.2 PA.3 17 18 19 20 I 21 22 23 24 25 26 47 48 49 50 63 64 1 2 I/O I/O 4-bit input-output ports. In input mode, pull-up resistor input or high-impedance input is selectable for each bit. In output mode, N-channel open drain output or CMOS output is selectable for each bit. Note that these pins are available for only a 64-pin package. O 4-bit output port. N-channel open drain output.
Function
Symbol P6.0 P6.1
Type
Description 4-bit input-output port. In input mode, pull-up resistor input or high-impedance input is selectable for each bit. In output mode, N-channel open drain output or CMOS output is selectable for each bit. Note that these pins are available for only a 64-pin package. 4-bit input port. Pull-up resistor input or high-impedance input is selectable for each bit.
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Table 2 shows the secondary functions of each pin of the ML63512A/63514A. Table 2 Pin Descriptions (Secondary Functions)
Pin TB 37 TP 51
Function
Symbol
Type
Description External 0 interrupt input pin.
P0.0/INT0
I
Edge detection can be selected from one of a rising edge, a falling edge, or both rising and falling edges. External 1 interrupt input pin.
P0.1/INT1 External Interrupt P0.2/INT2
38
52
I
Edge detection can be selected from one of a rising edge, a falling edge, or both rising and falling edges. External 2 interrupt input pin.
39
53
I
Edge detection can be selected from one of a rising edge, a falling edge, or both rising and falling edges. External 3 interrupt input pin.
P0.3/INT3 P1.0/TM0CAP P1.1/TM1CAP P1.0/TM0OVF Timer P1.1/TM1OVF P1.2/T0CK P1.3/T1CK Oscillation P2.0/TBCCLK Output P2.1/HSCLK P3.0/RXD
40 41 42 41 42 43 44 45 46 1
54 55 56 55 56 57 58 59 60 3
I I I O O I I O O I
Edge detection can be selected from one of a rising edge, a falling edge, or both rising and falling edges. Timer 0 (TM0) capture trigger input pin. Timer 1 (TM1) capture trigger input pin. Timer 0 (TM0) overflow flag output pin. Timer 1 (TM1) overflow flag output pin. Timer 0 (TM0) external clock input pin. Timer 1 (TM1) external clock input pin. Low-speed oscillation clock output pin. High-speed oscillation clock output pin. Serial port receive data input pin. Sync serial port clock input-output pin. Transmit sync clock input-output pin when a serial port is used
Capture
P3.1/TXC Serial Port P3.2/RXC
2
4
I/O
synchronously. Transmit clock output when this device is used as a master processor. Transmit clock input when this device is used as a slave processor. Sync serial port clock input-output pin. Receive sync clock input-output pin when a serial port is used
3
5
I/O
synchronously. Receive clock output when this device is used as a master processor. Receive clock input when this device is used as a slave processor.
P3.3/TXD Comparator Level Detector P7.0/CMPIN P7.1/CMPREF P7.2/LDIN0 P7.3/LDIN1
4 13 14 15 16
6 19 20 21 22
O I I I I
Serial port transmit data output pin. Comparator analog input pin. Comparator reference voltage input pin. Level detector analog input pin. Level detector analog input pin.
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Semiconductor
ML63512A/63514A
ABSOLUTE MAXIMUM RATINGS
(VSS = 0 V) Parameter Power Supply Voltage 1 Power Supply Voltage 2 Power Supply Voltage 3 Power Supply Voltage 4 Input Voltage 1 Input Voltage 2 Output Voltage 1 Output Voltage 2 Output Voltage 3 Storage Temperature Power Dissipation Symbol VDD VDDI VDDH VDDL VIN1 VIN2 VOUT1 VOUT2 VOUT3 TSTG PD Condition Ta = 25C Ta = 25C Ta = 25C Ta = 25C VDD Input, Ta = 25C VDDI Input, Ta = 25C VDD Output, Ta = 25C VDDI Output, Ta = 25C VDDH Output, Ta = 25C -- Ta = 25C Rating -0.3 to +5.8 -0.3 to +5.8 -0.3 to +5.8 -0.3 to +5.8 -0.3 to VDD + 0.3 -0.3 to VDDI + 0.3 -0.3 to VDD + 0.3 -0.3 to VDDI + 0.3 -0.3 to VDDH + 0.3 -55 to +150 60 Unit V V V V V V V V V C mW
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RECOMMENDED OPERATING CONDITIONS
* When backup is used
(VSS = 0 V) Parameter Operating Temperature Operating Voltage Crystal Oscillation Frequency Low-Speed RC Oscillator Frequency External High-Speed RC Oscillator Resistance Symbol Top VDD VDDI fXT fCRL RCRH Condition -- -- -- -- RCRL = 1 MW 10% VDD = 0.9 to 1.8 V Range -20 to +70 0.9 to 1.8 0.9 to 3.5 30 to 80 32 100 to 300 Unit C V V kHz kHz kW
* When backup is not used
(VSS = 0 V) Parameter Operating Temperature Symbol Top VDD VDDI Crystal Oscillation Frequency Low-Speed RC Oscillator Frequency External High-Speed RC Oscillator Resistance Ceramic Oscillation Frequency fXT fCRL RCRH fCM Condition -- -- Operating Voltage When Level detector and Comparator are not used -- -- RCRL = 1 MW 10% VDD = 1.8 to 5.5 V VDD = 2.2 to 5.5 V VDD = 2.7 to 5.5 V Range -20 to +70 1.8 to 3.5 1.8 to 5.5 1.8 to 5.5 30 to 80 32 15 to 300 300k to 1M 200k to 2M kHz kHz kW Hz V Unit C
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ELECTRICAL CHARACTERISTICS
DC Characteristics * When backup is used
(VDD = VDDI = 1.5 V, VSS = 0 V, Ta = -20 to +70C unless otherwise specified) MeaSymbol Condition Min. Typ. Max. Unit suring Circuit 4.8 5.3 Ta = 25C 5.8 CPU is in HALT state 5.3 9.0 mA IDD1 High-speed oscillation stop Ta = -20 to +50C -- Level detector stop 5.3 15.0 Ta = -20 to +70C -- Ta = 25C 12.0 13.0 14.0 CPU operating 13.0 16.0 mA IDD2 High-speed oscillation stop Ta = -20 to +50C -- Level detector stop Ta = -20 to +70C -- 13.0 24.0 1 CPU operating at low speed IDD3 High-speed oscillation stop Level detector active (for a soft duty of about 3%) CPU operating at high speed High-speed RC oscillation RCRH = 100 kW -- 10.0 35.0 mA
Parameter
Supply Current 1
Supply Current 2
Supply Current 3
Supply Current 4
IDD4
--
550.0 750.0
mA
* When backup is not used
(VDD = VDDI = 3.0 V, VSS = 0 V, Ta = -20 to +70C unless otherwise specified) MeaSymbol Condition Min. Typ. Max. Unit suring Circuit 2.1 2.4 Ta = 25C 2.7 CPU is in HALT state 2.4 7.0 mA IDD1 High-speed oscillation stop Ta = -20 to +50C -- Level detector stop 2.4 10.0 Ta = -20 to +70C -- Ta = 25C 5.0 6.0 7.0 CPU operating 6.0 9.0 High-speed oscillation stop Ta = -20 to +50C -- mA IDD2 Level detector stop Ta = -20 to +70C -- 6.0 15.0 IDD3 CPU operating at low speed High-speed oscillation stop Level detector active (for a soft duty of about 3%) CPU operating at high speed High-speed RC oscillation RCRH = 100 kW CPU operating at high speed High-speed ceramic oscillation (ceramic oscillation, 2 MHz) -- 6.0 25.0 1
Parameter
Supply Current 1
Supply Current 2
Supply Current 3
mA
Supply Current 4
IDD4
--
410.0 550.0
mA
Supply Current 5
IDD5
--
850.0 1000.0 mA
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Semiconductor
ML63512A/63514A
DC Characteristics (continued)
(VDD = VDDI = 1.5 V, VSS = 0 V, Ta = -20 to +70C unless otherwise specified) Parameter (Pin Name) Symbol Condition High-speed clock stop VDDH Voltage VDDH VDD = 1.5 V High-speed clock oscillation (RC oscillation, RCRH = 100 kW) VDDL Voltage Crystal Oscillation Start Voltage Crystal Oscillation Hold Voltage External Crystal Oscillator Capacitance Internal Crystal Oscillator Capacitance Internal Low-Speed RC Oscillator Capacitance Internal High-Speed RC Oscillator Capacitance Input Pin Capacitance (P0.0 to P0.3) (P1.0 to P1.3) CIN -- -- -- 5.0 pF (P7.0 to P7.3) (P9.0 to P9.3) (PA.0 to PA.3)
***
MeaMin. Typ. Max. Unit suring Circuit 2.8 2.0 1.0 2.0 1.2 0.9 5.0 20.0 10.0 8.0 -- -- 1.5 -- -- -- -- 25.0 15.0 12.0 3.0 -- 2.0 2.7 -- -- 25.0 30.0 20.0 16.0 V V V V V V pF pF pF pF 1
VDDL VSTA VHOLD CG CD CXT COS
High-speed clock stop High-speed clock oscillation Oscillation start time: within 5 seconds -- -- -- -- --
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DC Characteristics (continued)
(VDD = VDDI = 1.5 V, VSS = 0 V, Ta = -20 to +70C unless otherwise specified) Parameter (Pin Name) Output Current 1 (P0.0 to P0.3) (P1.0 to P1.3) (P6.0 to P6.3) (P9.0 to P9.3) (PA.0 to PA.3) (MD) Output Current 2 (P8.0 to P8.3) IOL2 Output Current 3 (OSC1) VOL2 = 0.5 V *** Symbol Condition VDD = 1.5 V IOH1 VOH1 = VDD - 0.5 V VDD = 3.0 V VDD = 5.0 V VDD = 1.5 V IOL1 IOH2Z VOL1 = 0.5 V VOH2 = VDD VDDI = 1.5 V VDDI = 3.0 V VDDI = 5.0 V IOH3R IOL3R IOH3C IOL3C Output Leakage (P0.0 to P0.3) (P1.0 to P1.3) (P6.0 to P6.3) (P8.0 to P8.3) (P9.0 to P9.3) (PA.0 to PA.3) *** VOH3R = VDDH - 0.5 V VOL3R = 0.5 V VOH3C = VDDH - 0.5 V VOL3C = 0.5 V VDD = VDDH = 3.0 V VDD = VDDH = 5.0 V VDD = VDDH = 3.0 V VDD = VDDH = 5.0 V VDD = VDDH = 3.0 V VDD = VDDH = 5.0 V VDD = VDDH = 3.0 V VDD = VDDH = 5.0 V VDD = 3.0 V VDD = 5.0 V MeaMin. Typ. Max. Unit suring Circuit -2.5 -1.3 -0.2 mA -6.0 -8.5 0.2 1.0 1.5 -- 3.0 6.0 8.0 -2.5 -3.5 0.2 0.5 -3.5 -5.0 1.3 3.0 3.7 -- 7.5 12.0 15.0 -1.5 -1.8 1.5 1.8 -1.0 -1.5 2.5 6.0 8.5 1.0 14.0 20.0 28.0 -0.2 -0.5 2.5 3.5 -60 300 400 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA 2
-300 -160 60 100 170 210
-400 -240 -100
IOOH
VOH = VDD
--
--
1.0
mA
IOOL
VOL = VSS
-1.0
--
--
mA
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Semiconductor
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DC Characteristics (continued)
(VDD = VDDI = 1.5 V, VSS = 0 V, Ta = -20 to +70C unless otherwise specified) Parameter (Pin Name) Input Current 1 (P0.0 to P0.3) (P1.0 to P1.3)
***
Symbol IIH1U IIL1U IIH1Z IIL1Z IIH2 IIL2
Condition VIH1 = VDD (when pulled up) VIL1 = VSS (when pulled up) VDD = 1.5 V VDD = 3.0 V VDD = 5.0 V
MeaMin. Typ. Max. Unit suring Circuit -- -8.0 -- -4.0 1.0 -1.0 mA mA
-60.0 -30.0 -10.0 mA -150.0 -90.0 -23.0 mA -- -1.0 -- -- -- -- 1.0 -- 1.0 mA mA mA mA 3
(P7.0 to P7.3) (P9.0 to P9.3) (PA.0 to PA.3) Input Current 2 (RESETB)
VIH1 = VDD (in a high-impedance state) VIL1 = VSS (in a high-impedance state) VIH2 = VDD VIL2 = VSS (when pulled up) VIL3 = VSS (when pulled up) VIH3 = VDDH VIL3 = VSS VIH4 = VDD VIL4 = VSS (when pulled up) VDD = 1.5 V VDD = 3.0 V VDD = 5.0 V VDD = 1.5 V VDD = 3.0 V VDD = 5.0 V
-45.0 -20.0 -2.0
-260.0-120.0 -30.0 mA -870.0-300.0 -70.0 mA
Input Current 3 (OSC0)
IIL3 IIH3R IIL3R
VDD = VDDH = 3.0 V -350.0-170.0 -30.0 mA VDD = VDDH = 5.0 V -750.0-450.0 -200.0 mA -- -1.0 -- -- -- -- 1.0 -- 0.1 mA mA mA
Input Current 4 (TST1B, TST2B)
IIH4 IIL4
-120.0 -60.0 -10.0 mA -600.0-350.0 -100.0 mA -1320.0 -770.0 -220.0 mA
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Semiconductor DC Characteristics (continued)
ML63512A/63514A
(VDD = VDDI = 1.5 V, VSS = 0 V, Ta = -20 to +70C unless otherwise specified) Parameter (Pin Name) Input Voltage 1 (P0.0 to P0.3) (P1.0 to P1.3) (P7.0 to P7.3) (P9.0 to P9.3) (PA.0 to PA.3) Input Voltage 2 (OSC0) Symbol VDD = 1.5 V VIH1 VDD = 3.0 V VDD = 5.0 V VDD = 1.5 V VIL1 VDD = 3.0 V VDD = 5.0 V VIH2 VIL2 Input Voltage 3 (RESETB) (TST1B, TST2B) VIH3 VDD = VDDH = 3.0 V VDD = VDDH = 5.0 V VDD = VDDH = 3.0 V VDD = VDDH = 5.0 V VDD = 1.5 V VDD = 3.0 V VDD = 5.0 V VDD = 1.5 V VIL3 Hysteresis Width (P0.0 to P0.3) (P1.0 to P1.3) (P7.0 to P7.3) (P9.0 to P9.3) (PA.0 to PA.3) (RESETB) (TST1B, TST2B) VDD = 3.0 V VDD = 5.0 V VDD = 1.5 V Condition MeaMin. Typ. Max. Unit suring Circuit 1.2 2.4 4.0 0.0 0.0 0.0 2.4 4.0 0.0 0.0 1.35 2.4 4.0 0.00 0.0 0.0 0.05 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.10 1.5 3.0 5.0 0.3 0.6 1.0 3.0 5.0 0.6 1.0 1.50 3.0 5.0 0.15 0.6 1.0 0.30 V V V V V V V V V V V V V V V V V 4
***
***
VT
VDD = 3.0 V
0.2
0.5
1.0
V
VDD = 5.0 V
0.25
1.00
1.50
V
17/29
Semiconductor Hysteresis width
ML63512A/63514A
Input Signal
VT
VDD VSS
Internal Signal
VDDL VSS
18/29
Semiconductor Measuring circuit 1
ML63512A/63514A
*1
q w
XT0 XT1
CB1 Cb12 CB2
*2
e r
OSC0 OSC1 VSS VDD A VDDI VDDH Ch V VDDL Cl V : 15 pF CG Cb12, Ch : 1 mF : 0.1 mF Cl : 12 pF CO Ceramic Resonator : CSA2.00MG (2 MHz) CSB1000J (1 MHz) (Murata MFG.-make) : 30 pF CL0 : 30 pF CL1
*1 RC oscillator q RCRL w
*2 RC oscillator e RCRH r
Crystal oscillator CG q w
Ceramic oscillator CL0 CL1 e Ceramic resonator r
19/29
Semiconductor
ML63512A/63514A
Measuring circuit 2
*4 VIH
*3
INPUT
OUTPUT
A
VIL
VSS
VDD
VDDI
VDDH
VDDL
*3 Input logic circuit to determine the specified measuring conditions. *4 Measured at the specified output pins.
Measuring circuit 3
*5
A
INPUT
OUTPUT
VSS
VDD
VDDI
VDDH
VDDL
20/29
Semiconductor Measuring circuit 4
ML63512A/63514A
VIH
*5
INPUT
OUTPUT
Waveform Monitoring
VIL
VSS
VDD
VDDI
VDDH
VDDL
*5 Measured at the specified input pins.
21/29
Semiconductor
ML63512A/63514A
AC Characteristics (Serial Interface, Serial Port) (VDD = 0.9 to 5.5 V, VDDH = 1.8 to 5.5 V, VSS = 0 V, VDDI = 0.9 to 5.5 V, Ta = -20 to +70C unless otherwise specified) (1) Synchronous Communication
Parameter TXC/RXC Input Fall Time TXC/RXC Input Rise Time TXC/RXC Input "L" Level Pulse Width TXC/RXC Input "H" Level Pulse Width TXC/RXC Input Cycle Time TXC/RXC Output Cycle Time TXD Output Delay Time RXD Input Setup Time RXD Input Hold Time Symbol tf tr tCWL tCWH tCYC tCYC1(O) tCYC2(O) tDDR tDS tDH Condition -- -- -- -- -- CPU operating at 32.768 kHz CPU operating at 2 MHz VDD = VDDH = 2.7 to 5.5 V Output load capacitance 10 pF -- -- Min. -- -- 0.8 0.8 2.0 -- -- -- 0.5 0.8 Typ. -- -- -- -- -- 30.5 0.5 -- -- -- Max. 1.0 1.0 -- -- -- -- -- 0.4 -- -- Unit ms ms ms ms ms ms ms ms ms ms
Synchronous communication timing ("H" level = 4.0 V, "L" level = 1.0 V)
tCYC TXC (P3.1)/ RXC (P3.2) tr tCWH tDDR TXD (P3.3) tDS RXD (P3.0) tDH tDS VDD (5.0 V) VSS tDDR VDD (5.0 V) VSS tf tCWL VDD (5.0 V) VSS
22/29
Semiconductor (2) UART Communication
ML63512A/63514A
Parameter Transmit Baud Rate Receive Baud Rate
Symbol TBRT RBRT
Condition TBRT = 1/fBRT TCR = 1/fOSC RBRT = 1/fBRT
Min. TBRT-TCR RBRT0.97
Typ. TBRT RBRT
Max. TBRT+TCR RBRT1.03
Unit s s
fBRT: Baud rates (2TBCCLK, TBCCLK, 1/2TBCCLK, Timer 0/1 overflow)
UART communication timing ("H" level = 4.0 V, "L" level = 1.0 V)
TBRT TXD (P3.3) RBRT RXD (P3.0) VDD (5.0 V) VSS VDD (5.0 V) VSS
23/29
Semiconductor
ML63512A/63514A
AC Characteristics
(VDD = VDDI = 0.9 to 5.5 V, VSS = 0 V, Ta = -20 to + 70C unless otherwise specified) Parameter External Interrupt Enable Pulse Width (Rising Edge) External Interrupt Enable Pulse Width (Falling Edge) External Interrupt Disable Time Symbol tWH tWL Condition -- -- Interrupt enable, MIE = 1 CPU operating under the NOP instruction System clock: 32.768 kHz Min. 20 20 Typ. -- -- Max. -- -- Unit ns ns
tNUL
13.0
--
65.1
ms
AC characteristics timing
P0.0 to P0.3 (Interrupt on the rising edge) tWH tNUL P0.0 to P0.3 (Interrupt on the falling edge) tWL tNUL
P0.0 to P0.3 (Interrupt on both rising and falling edges) tNUL
24/29
Semiconductor Comparator Electrical Characteristics
ML63512A/63514A
(VDD = 0.9 V, VSS = 0 V, Ta = -20 to +70C) Parameter Comparator Offset Voltage Comparator Input Voltage Comparator Conversion Time Comparator Supply Current Symbol Vcoff Vcin TC IDDCMP IDSCMP Condition -- -- System clock: 32.768 kHz Comparator operating Comparator stopped Min. -- VSS -- -- -- Typ. -- -- 183 30 -- Max. 30 VDD -- 90 0.1 Unit mV V ms mA mA Remarks
CMPIN CMPREF
Conceptual diagram of comparator supply current The conceptual diagram of the comparator supply current IDDCMP and IDSCMP is shown below.
IDD (VSS) [mA]
IDDCMP
IDSCMP Sampling reference voltage Comparing reference voltage with input voltage t [ms]
Level detector stopped
Level detector operating
Level detector stopped
25/29
Semiconductor Level Detector Electrical Characteristics
ML63512A/63514A
(VDD = 0.9 V, VSS = 0 V, Ta = -20 to +70C) Parameter Level Detector Input Voltage Level Detector Conversion Time Level Dtector Supply Current Symbol VLD TC IDDLD IDSLD Condition -- System clock: 32.768 kHz Level detector operating Level detector stopped Min. VSS -- -- -- Typ. -- 183 80 -- Max. VDD -- 130 0.1 Unit V ms mA mA LDIN0, 1 Remarks
Conceptual diagram of level detector supply current The conceptual diagram of the level detector supply current IDDLD and IDSLD is shown below.
IDD (VSS) [mA]
IDDLD
IDSLD Sampling reference voltage Comparing reference voltage with input voltage t [ms]
Level detector stopped
Level detector operating
Level detector stopped
26/29
Semiconductor Level Detector Input Levels and Output Codes
ML63512A/63514A
(VDD = 0.9 to 1.8 V: when backup is used, VDD = 1.8 to 3.5 V: when backup is not used; VSS = 0 V, Ta = -20 to +70C)
Input Level [V] Min. 1440/1500 VDD 1306/1500 VDD 1190/1500 VDD 1074/1500 VDD 958/1500 VDD 842/1500 VDD 726/1500 VDD 610/1500 VDD 494/1500 VDD 378/1500 VDD 262/1500 VDD 146/1500 VDD VSS Max. VDD 1366/1500 VDD 1250/1500 VDD 1134/1500 VDD 1018/1500 VDD 902/1500 VDD 786/1500 VDD 670/1500 VDD 554/1500 VDD 438/1500 VDD 322/1500 VDD 206/1500 VDD 88/1500 VDD ON state Level Detector Operation State OFF state bit 3 1 1 1 1 1 0 0 0 0 0 0 0 0 LDOUT bit 2 1 0 0 0 0 1 1 1 1 0 0 0 0 bit 1 1 1 1 0 0 1 1 0 0 1 1 0 0 bit 0 1 1 0 1 0 1 0 1 0 1 0 1 0
27/29
Semiconductor
ML63512A/63514A
PACKAGE DIMENSIONS
(Unit : mm)
TQFP48-P-0707-0.50-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.13 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
28/29
Semiconductor
ML63512A/63514A
(Unit : mm)
TQFP64-P-1010-0.50-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.26 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
29/29
E2Y0002-29-62
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. MS-DOS is a registered trademark of Microsoft Corporation.
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Copyright 1999 Oki Electric Industry Co., Ltd.
Printed in Japan

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